Logica programavel

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FERRAMENTAS PARA PROJETOS 
DE SISTEMAS DIGITAIS
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Circuito Lógico
� Equações 
x1 = A * B + C * !D
� Circuitos Portas e flip-flops
� Componentes std
74xx, 4xxx …
COUNTER
CLRN
CLK
ENP
LDN
A
D
ENT
B
C
QD
QC
QB
QA
RCO
74161
inst10
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7490
Lógicas Programáveis
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Lógica Programável
Lembrete :
A * 1 = A
A * /A = 0
A + 0 = A
XA
B
1*/A*B*1 = /A*B
fusíveis
X
B
A*/A*B*/B = 0
/A*B + 0 = /A*B 
S
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Tipos – lógicas programáveis
� PAL - Programmable array logic
� 1978 Monolithic Memories, Inc. (MMI)
� GAL - Generic array logic
� Lattice Semiconductor.
� EPLD - Erasable Programmable Logic Device� EPLD - Erasable Programmable Logic Device
� ALTERA
� CPLD - Complex Programmable Logic Device
� ALTERA / xilinx
� FPGA - Field Programmable Gate Array
� ALTERA / xilinx
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PAL16R4
fusíveis
Várias entradas
fusíveis
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GAL16V8 - Lattice
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EPLD – EP610 - ALTERA
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CPLD – EPM7064 - ALTERA
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CPLD – Macrocell - ALTERA
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CPLD – ISP in-system programmability
Mount Unprogrammed Program In-System Reprogram in the Field
� No Device Handling
� No Bent Leads
� Allows Generic 
Inventory
� Prototyped Easily
� Supports Changes 
During Manufacturing/ 
Test Flow
� Allows Field Upgrades
� Adds Enhancements 
Quickly & Easily
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FPGA – equação lógica
D C B A S
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
Função lógica
Gera uma 
Tabela Verdade
TV
Memoria
A
B
C
S
Dados=Resultado
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
Memoria
RAM
(LUT)
D
Entrada=endereços
LUT= Look Up Table 
S
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FPGA – Spartan 3 - XILINX 
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FPGA – Stratix ALTERA
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FPGA – ISP / Configuration
FPGA – Stratix - ALTERA
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Stratix Architecture Overview
Logic Array
Blocks (LABs)
DSP Blocks
M-RAM
Blocks
M512 RAM 
Blocks
Phase-Locked
Loops (PLLs)
M4K RAM
Blocks
I/O Elements
(IOEs)
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TriMatrix Memory
M4K BlocksM512 Blocks
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