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Step 1 of 2 8.037E Draw the cascading scheme of 36-bit synchronous parallel counter using nine 74x163 (4-bit binary counter). +5 V CLOCK LD Q0 c Q1 Q2 8 Q3 as as LD CLR Q4 c Q5 LD CLR Q20 & : Q21 8 Q7 A Q22 8 Q23 as ENT LD Q8 Q9 9 as Q24 A Q10 : Q25 8 Q11 A Q26 8 Q27 as as LD Q12 : Q13 as Q28 A Q14 : Q29 8 Q15 A Q30 8 Q31 as LD CLR Q16 c Q17 9 Q32 A Q18 : Q33 8 Q19 034 8 Q35 Figure 1 Step 2 of 2 In Figure 1, Q35 is the MSB and Q0 is the LSB. The counting starts from 000000000000000000000000000000000000 and ends at 111111111111111111111111111111111111, thus covering all the states. From the manufacturer's data sheet consider the following data: The propagation delay of 74x163 is 14 nS. The maximum clock frequency is 32 MHz. Time period of one clock cycle is, 1 = 31 ns 32 MHz Determine the counting speed per instruction. Time period + propagation delay 31 + 14 = 45 ns Thus, the maximum counting speed is 45 ns