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Step 1 of 1 5.12DP In a Verilog program, if multiple values are assigned to the same signal in a Verilog combinational always block. When it completes the execution, the signal value is the last value assigned. Because in the combinational logic always block, blocking assignment operator is used '=' and it makes the steps to be executed sequentially. So the last value assigned will be the signal's value. Thus, the correct option is (c) the last value assigned