Chegg Solutions for Microelectronic Circuits (Adel S Sedra, Kenneth C Smith) (Z-Library)_parte_1735

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Step of 5 16.003P The logic gate implementation of SR flip-flop using NAND gate is, So G₁ Q Ro G₂ Figure 1 Step of 5 The following is the truth table for the flip-flop: Table 1 R 0 0 Not used 0 1 0 1 0 1 1 1 Step of 5 Operation: The set and reset functions are active when low for the flip-flop implemented by cross-coupling of NAND gates. Similar to the state of the SR flip-flop using cross-coupled NOR gate, in active low SR flip- flop the = R = 0 state is an undefined state and it cannot be used. When R=0 = and if = then the inputs to 2 are, R = and = Therefore, The inputs to are, and Therefore, = Alternatively if = then inputs to are, R and = Therefore, The inputs to are, and Therefore, = Thus, for S=1 = and = irrespective of the present state the output, goes to reset state, Step of 5 When = R=1 and if = then the inputs to are, = and = Therefore, =1. The inputs to are, and Therefore, Alternatively if then inputs to are, and = Therefore, The inputs to are, = and =1. Therefore, Thus, for S=0 and R=1 irrespective of the present state the output, goes to set state, Step 5 of 5 If = = and if = then the inputs to are R=1 and Therefore, = The inputs to are, and = Therefore, Alternatively if then inputs to are, and = Therefore, The inputs to are, = and =1. Therefore, Thus, for S=1 and R = irrespective of the present state the output, remains in same state,