ENERGY OPTIMIZATION OF TAPERED BUFFERS

Prévia do material em texto

ENERGY OPTIMIZATION OF TAPERED BUFFERS 
FOR CMOS ON-CHIP SWITCHING POWER CONVERTERS 
 
G.Villar, E. Alarcón, J. Madrenas, F. Guinjoan, A. Poveda 
 
Department of Electronic Engineering 
Universitat Politècnica Catalunya 
08034 Barcelona, Spain. 
e-mail: gvillar@eel.upc.edu 
 
ABSTRACT 
This work presents a model to determine the power 
consumption of tapered buffers, validating its results with 
transistor-level simulations. Focusing on their application as 
gate drivers for high-frequency on-chip switching power 
converters, the need for a fall-rise time evaluation at the 
output of the tapered buffer will be discussed. Consequently, 
output fall-rise time is modeled and validated by means of 
simulations. Given the linear relation between the fall-rise 
time and the switching losses of the power MOSFET, it is 
proposed an optimized design procedure to concurrently 
minimize the switching losses of the tapered buffer together 
with the power MOSFET switching losses. The work concludes 
with a design example for a 15000µm-width PMOS transistor, 
presenting an optimum tapering factor of 21, for a specific 
0.35µm standard CMOS technology. 
1. INTRODUCTION 
The current trend towards an increase of computing capability 
in portable devices such as mobile phones, PDAs and personal 
music players contrasts with the continuous reduction of their 
volume and weight, as well as the demand for a longer 
operating life. Similarly, in a lower level of abstraction, there 
is a rather direct relation between the computing capability of 
these devices and their power consumption, while the energy 
management systems (battery and power supply circuits) are 
key for efficiency and become a significant portion of the 
overall volume and weight. 
Therefore, efficient energy management circuits with reduced 
volume and weight are required. The most efficient energy 
conversion from a DC source (such as a battery) is achieved by 
means of switching power converters, but their main drawback 
is that they are bulky. Thus, the development of fully 
integrated switching power converters is of key interest. On 
the other hand, an expected high frequency operation is 
derived from the reduction of their reactive components, which 
is detrimental to high efficiency due to increased switching 
losses that might preclude their practical application. 
In figure 1 the basic scheme of a switching buck converter is 
presented. The main conduction losses are due to parasitic 
series resistances of the power transistors, the inductor and the 
capacitor. The switching losses basically appear in the power 
transistors (MOSFET in the case of standard CMOS 
technologies), in the inductor (due to the magnetic hysteresis 
cycle of the ferromagnetic core, if any), and notably in the 
power gate drivers that activate the power transistor gates. Due 
to high frequency operation, switching losses can not be 
neglected. Since switching losses in the inductor depend on the 
material that builds up the ferromagnetic core, which is not 
available in a standard CMOS process, the presented work 
does not take them into account and is focused towards the 
minimization of switching losses in power transistors and their 
associated drivers, by means of their concurrent design. 
 L 
C 
iL 
vout 
+
-
iout 
D
R
IV
ER
 
D
R
IV
ER
 
d(t)
BA
TT
ER
Y 
switching 
losses 
conduction + switching 
losses
joined 
design
 
Fig.1.- Gate driver and power transistor switching losses 
 in a buck converter 
In standard CMOS processes, the power of the switching 
signal is commonly amplified by a chain of digital inverters 
having their transistors an increasing channel width. This is 
known as tapered buffer structure (figure 2), being the tapering 
factor (f) the value that scales the transistors channel width in 
two consecutive inverters. 
Eout 
Ein 
in
out
E
EefficiencyOverall =_ 
1 f f n-1 f n
vin Power 
MOSFET
f 2
 
Fig. 2.- Overall energy consumption in a tapered buffer and 
 the corresponding power MOSFET 
Tapered buffers have been historically developed and analyzed 
in the literature mainly in the field of drivers for digital IC 
pads. In 1975 Lin and Linholm [1] proposed a delay model 
based on the propagation delay between two minimum 
inverters and Jaeger [2] found the optimum tapering factor that 
minimized the total propagation delay. Afterwards, Nemes [3] 
added the concept of parasitic delay of an inverter without 
load. Subsequently, Li et al. [4] used the split-capacitor model 
to determine the total propagation delay of a tapered buffer. In 
1991, Sutherland [5] introduced the delay estimation by means 
of the logical effort concept. 
Although all these works deeply analyzed the propagation 
delay of tapered buffers, energy consumption is of paramount 
interest in high frequency switching power converters 
application. Fewer works have studied the power consumption 
of these circuits. Choi and Lee [6] proposed a capacitive 
44530-7803-8834-8/05/$20.00 ©2005 IEEE.
approach based on the split-capacitor model. Cherkauer and 
Friedman [7] added to the capacitive approach the short-circuit 
current estimation based on the Sakurai short-channel α-power 
model of transistor operation [8]. 
More recently, contributions about tapered buffer design 
focused on their application to switching power converters 
have been reported (Stratakos [9], Kursun [10]) proposing 
tapering factor values that aim to reduce the corresponding 
switching losses. 
This work proposes an energy model, analogous to the Nemes 
delay model [3], to determine the energy consumption of a 
tapered buffer (section 2). In addition to this, in section 3 a 
fall-rise time model of a tapered buffer is proposed, showing 
that it is related to the switching losses of the power MOSFET. 
A design procedure for the tapered buffer that concurrently 
minimizes both driver losses and switching losses of power 
MOSFET is discussed in section 4. Finally, a design example 
for a given power MOSFET in a 0.35µm CMOS standard 
technology is exposed in section 5. 
2. PROPOSED SWITCHING ENERGY 
LOSS MODEL 
The proposed energy model is based on the amount of charge 
required to change the state of a digital inverter. Charge is 
observed rather than current because for switching losses 
evaluation it is more convenient to model the energy (that 
depends on voltage and charge) spent in each switching cycle 
than to model the power, since the power changes with 
switching frequency. 
Both intrinsic charge and unitary effort charge concepts 
(figure 3) are used to determine the total charge spent in a 
switching cycle by a single stage of the inverter chain: 
Switching charge = f i-1Qi +f i Qe1 (1) 
1. Intrinsic charge (Qi): due to charge from Vss to Vdd in a 
unitary inverter during a state transition. 
2. Unitary effort charge (Qe1): due to the additional charge 
from Vdd during the state transition, when a unitary 
inverter is loaded with an identical inverter. 
1 
vin 
tfri 
Qi 
1 1
vin 
tfri+tfre1 
Qi+ Qe1 
 
Fig. 3.- Measurement tests of intrinsic and unitary effort charge, 
 and fall-rise time 
In expression (1), f represents the tapering factor, and i is the 
exponent corresponding to the i-th stage, being the first one 
i=1. 
The total charge supplied from the voltage source to the whole 
n-inverters chain is: 
( )
f
ffQQfQ
f
Q
QQQQ
n
ei
n
i
i
e
i
nT −
−
+=





+=+++= ∑
= 1
1.... 1
1
121
(2) 
And consequently the energy consumption is given by: 
( )
1
1
1 −
−
+=
f
ffQQVE
n
eiDDdriver
 (3) 
The most common definition of the tapering factor [3] is found 
as the ratio between the equivalent input capacitance of the 
first stage, and the equivalent input capacitance of the target 
load (the power MOSFET gate in the application under study). 
n
in
out
C
C
f =
 (4) 
Because of the planar capacitor associated with the transistor 
gate in standard CMOS technology, the output-to-input 
capacitors ratioof the inverters chain can be expressed in 
terms of the dimensions, and in turn in terms of their 
corresponding channel widths, which is more useful in the 
design step: 
n
np
power
n
npox
powerox
WW
W
LWWC
LWC
f
)()( +
=
+
=
 (5) 
being Wpower the channel width of the power MOSFET, and Wp 
and Wn the channel width of the P-MOS and N-MOS of the 
input inverter, respectively. 
In order to validate the model, the results from equation (3) are 
compared with transistor-level simulation results for a 
particular 0.35 µm CMOS technology. In figure 4, the 
evolution of energy consumption for several inverter chains 
with different number of stages is shown. In all cases, the 
output load is a 15000 µm – width PMOS transistor 
(corresponding to a conduction resistance of 0.4Ω), and the 
supply voltage is 3.6V (which is the nominal value of a Li-Ion 
battery). 
Simulation 
results
Model 
results 
 
Fig. 4.- Switching energy loss of tapered buffers as a function of 
 the number of stages (model and transistor-level simulation) 
Note that in case the load input capacitance can not be easily 
modeled (e.g. nonlinear capacitor), a more general definition 
of the tapering factor can be used. In that case, the n-root of 
the ratio between the charge spent to change the state of the 
load device, and the unitary effort charge is computed: 
n
e
out
Q
Qf
1
=
 (6) 
3. PROPOSED FALL-RISE TIME 
MODEL 
Since current CMOS technology is able to operate at switching 
frequencies (GHz) well above of those required by switching 
power converters (even in case of high frequency designs to be 
integrated, in the order of tens of MHz), the delay across the 
whole tapered buffer becomes of low relative significance. 
Consequently, taking into account the monotonic evolution of 
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power consumption as the number of inverters in the chain 
increase, it might seem that the optimum design consists in a 
one-inverter tapered buffer. 
Nevertheless there is an additional factor to take into account 
in the design step. The switching losses of a power CMOS 
transistor depend on the time spent to change its state (the 
slower the transition occurs, the higher the switching losses 
are), which directly depends on the tapered buffer design. 
Thus, instead of delay time (td), the output fall-rise time (tfr) 
should be considered when designing a power-aware tapered 
buffer, assuming that both fall time and rise time are similar. 
The fall-rise time of the last stage of a tapered buffer can be 
approximated by means of the following expression: 
1frefrifr fttt += (7) 
where tfri is the fall-rise time of a single minimum sized 
inverter without load, and tfre1 is the unitary effort fall-rise time 
(additional transition time when a minimum inverter is 
connected to another one), as seen in previous figure 3. 
In figure 5 the proposed model results (7) and the transistor-
level simulation results are depicted, exhibiting a rather tight 
matching (especially for larger number of stages). 
Simulation 
results 
Model 
results 
 
Fig. 5.- Fall-rise time as a function of the number of stages 
As shown in the previous picture, the tfr increases as the 
number of inverters of the chain is reduced (and the 
corresponding tapering factor increases). This trend becomes 
clearer in the transient simulations of figure 8, where falling 
edge of the output is presented for several inverters chains 
(with the corresponding different tapering factors), keeping the 
power MOSFET size constant. 
4. ENERGY-AWARE OPTIMIZED 
DESIGN OF A TAPERED BUFFER 
DRIVING A POWER MOSFET 
The presence of two opposed trends in the dependence of 
power consumption and fall-rise time on the number of 
inverters in the tapered buffer chain, suggests the existence of 
an optimized design of the tapered buffer as regards energy 
consumption (this is, when aiming to minimize the overall 
switching losses encompassing tapered buffer and power 
transistor). 
To find this optimized design a relationship between fall-rise 
time and switching losses in the power transistor is required. 
From the 0.35 µm CMOS transistor-level simulation measures 
a rather linear function that relates the fall-rise time and the 
switching losses can be obtained (figure 6). 
( ) min1min ·· tefrefritetefrteSWPowerMOS EfttKEtKE ++=+=−
 (8) 
It should be noted that the Etemin and Kte terms are expected to 
depend on the transistor size, the technological process and 
switching conditions, and are obtained from simulation results. 
Simulation 
results 
Model 
results 
 
Fig. 6.- Power MOSFET switching losses 
as a function of the fall-rise time 
Resorting to the modeling provided by equations (8) and (3), 
an expression for the overall power consumption can be 
obtained: 
( ) ( )
f
ffQQVEfttKEEE
n
eiDDtefrefritedriverSWPowerMOST −
−
++++=+= − 1
1· 1min1
(9)
The simulation results showing the overall energy 
consumption as well as the results derived from the model (9) 
are shown in figure 7. It is observed the minimum generated 
by the two opposed trends in power consumption, namely from 
switching losses of the tapered buffer and from the power 
MOSFET. 
Simulation 
results 
Model 
results 
Qi = 12.25 fC 
Qe1 = 9.7 fC 
tfre1 = 40.2 ps 
tfri = 47.6 ps 
Kte = 64.83 mW 
Etemin = 148.1 pJ 
 
Fig. 7.- Total switching energy loss as a function of 
 the number of stages of the tapered buffer 
The last step is to substitute the tapering factor by its 
expression in terms of number of inverters n (as given in (4)). 
The number of inverters is preferred as a design variable 
because it is constrained to natural values, whereas f varies 
continuously. Finally, the optimized design of the tapering 
buffer that not only minimizes its own losses, but minimizes 
the power transistor switching losses hence achieving the 
global goal is obtained as: 







 +−
+
=
1
11 ))(1(
1log
)log(
frete
eiddfrete
opt
tK
QQaVtK
an
 
(10) 
where a is the Cout/Cin ratio (or Wpower/(Wp+Wn)). The result of 
expression (10) needs to be rounded to the nearest natural 
value. Note that a complete design procedure would choose the 
channel width for the power MOSFET that equalize 
conduction and switching losses. 
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5. DESIGN EXAMPLE 
An optimized design of a tapered buffer acting as gate drive 
for a power MOSFET in AMS 0.35µm CMOS standard 
process is presented in the following. The output power device 
is a PMOS transistor of 15000 µm /0.35 µm size, conducting a 
100mA current in its on state. 
Table 1 and table 2 present the values of all the required 
parameters for the selected technology. 
Wpower 15000µm Qi 12.25fC 
Wp 1.2µm Qe1 9.72fC 
Wn 0.4µm Kte 64.83mW 
VDD 3.6V tfre1 40.2ps 
Table 1.- Design parameters Table 2.-Model parameters 
(obtained by simulation) 
According to expression (10) and (5): 
3172.3 ≅=optn (11) 
08.21=optf (12) 
Note that this factor is notably higher than those presented in 
previous approach of tapered buffers operating as gate drivers 
(Stratakos [9], Kursun [10]). The resulting transistor sizes of 
all the inverters implementing the tapered buffer driving the 
power MOSFET are summarized in table 3 (only the channel 
width is shown, since the channel length is the same for all the 
transistors and equal to 0.35µm). 
Stage 1 2 3 
PMOS 1.2 µm 25.3 µm 533.55 µm 
NMOS 0.4 µm 8.45 µm 177.85 µm 
Table 3.- Transistor’s channel width of the optimized tapered buffer 
2-inverter E = 826 pJ 
3-inverter E = 591 pJ 
4-inverter E = 601 pJ 
90% 
10% 
 
Fig. 8.- Transistor-level transient simulation results. 
Instant dissipated power (tapered buffer + power MOSFET) 
 and fall and rise edges of the output signal 
Figure 8 depicts the fall and rise edges of the switching signal 
at the power transistor’s gate, for the designed 3-stage tapered 
buffer, and for the cases of 2-stage (f=96.8) and 4-stage 
(f=9.8). The overall instantaneous power (power MOSFET + 
tapered buffer) provided by the 3.6Vvoltage source, is 
included. 
From the previous results, it is observed that the best results as 
far as energy consumption is concerned are obtained by means 
of the 3-inverters tapered buffer, as predicted by (11). 
Additional design considerations should take into account that 
an increasing number of inverters increases the peak value of 
instant power, thus compromising reliability, which makes the 
3-stage design even better (in front of the 4-stage design). 
6. CONCLUSIONS 
A methodology to optimize the switching energy losses of 
power MOSFETs and their associated tapered buffers, 
targeting on-chip switching power converters application, has 
been proposed. The presented approach is derived from the 
modeling of the energy consumption of the tapered buffer by 
itself, and the repercussion of its output fall-rise time upon the 
switching losses of the power MOSFET. Both contributions to 
total switching losses present opposed trends as a function of 
the number of stages in the tapered buffers. Thus, a minimum 
is found from transistor level simulations results which 
coincides with that one arisen from the proposed model and 
design procedure. A design example has been carried out to 
validate the approach. The target load was a 15000µm-width 
PMOS transistor, in a proof-of-concept 0.35µm CMOS 
technology, and a tapering factor of 21 (for a 3-inverter chain) 
has been found as the best trade-off between tapered buffer 
switching losses and power transistor switching losses. 
Acknowledgements. This work has partially funded by 
projects TIC-2001-2183 and TIC-2001-2157-C02-01 from the 
Spanish MCYT. Gerard Villar holds a CICYT Research 
fellowship. 
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