Infineon-IRFI4019H-117P-DataSheet-v01_01-EN

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8/22/06
IRFI4019H-117P
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TO-220 Full-Pak 5 PIN
Features
� Integrated Half-Bridge Package
� Reduces the Part Count by Half
� Facilitates Better PCB Layout
� Key Parameters Optimized for Class-D
Audio Amplifier Applications
� Low RDS(ON) for Improved Efficiency
� Low Qg and Qsw for Better THD and
Improved Efficiency
� Low Qrr for Better THD and Lower EMI
� Can Delivery up to 200W per Channel into
8Ω Load in Half-Bridge Configuration
Amplifier
� Lead-Free Package
Description
This Digital Audio MosFET Half-Bridge is specifically designed for Class D audio amplifier applications. It
consists of two power MosFET switches connected in half-bridge configuration. The latest process is used
to achieve low on-resistance per silicon area. Furthermore, Gate charge, body-diode reverse recovery, and
internal Gate resistance are optimized to improve key Class D audio amplifier performance factors such
as efficiency, THD and EMI. These combine to make this Half-Bridge a highly efficient, robust and reliable
device for Class D audio amplifier applications.
G1, G2 D1, D2 S1, S2
Gate Drain Source
Absolute Maximum Ratings �
Parameter Units
VDS Drain-to-Source Voltage V
VGS Gate-to-Source Voltage
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
IDM Pulsed Drain Current �
EAS Single Pulse Avalanche Energy� mJ
PD @TC = 25°C Power Dissipation � W
PD @TC = 100°C Power Dissipation �
Linear Derating Factor W/°C
TJ Operating Junction and °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Thermal Resistance �
Parameter Typ. Max. Units
RθJC Junction-to-Case � ––– 6.9
RθJA Junction-to-Ambient � ––– 65
77
18
7.2
0.15
10lb�in (1.1N�m)
-55 to + 150
300
Max.
6.2
34
 ±20
150
8.7
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VDS 150 V
RDS(ON) typ. @ 10V 80 m�
Qg typ. 13 nC
Qsw typ. 4.1 nC
RG(int) typ. 2.5 Ω
TJ max 150 °C
Key Parameters �
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S
D
G
��Repetitive rating; pulse width limited by max. junction temperature.
� �Starting TJ = 25°C, L = 5.8mH, RG = 25Ω, IAS = 5.2A.
� Pulse width ≤ 400µs; duty cycle ≤ 2%.
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	 Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive
 avalanche information
 Specifications refer to single MosFET.
Electrical Characteristics @ TJ = 25°C (unless otherwise specified) �
Parameter Min. Typ. Max. Units
BVDSS Drain-to-Source Breakdown Voltage 150 ––– ––– V
∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.19 ––– V/°C
RDS(on) Static Drain-to-Source On-Resistance ––– 80 95 mΩ
VGS(th) Gate Threshold Voltage 3.0 ––– 4.9 V
∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -11 ––– mV/°C
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA
––– ––– 250
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
gfs Forward Transconductance 11 ––– ––– S
Qg Total Gate Charge ––– 13 20
Qgs1 Pre-Vth Gate-to-Source Charge ––– 3.3 –––
Qgs2 Post-Vth Gate-to-Source Charge ––– 0.8 ––– nC
Qgd Gate-to-Drain Charge ––– 3.9 –––
Qgodr Gate Charge Overdrive ––– 5.0 ––– See Fig. 6 and 19
Qsw Switch Charge (Qgs2 + Qgd) ––– 4.1 –––
RG(int) Internal Gate Resistance ––– 2.5 ––– Ω
td(on) Turn-On Delay Time ––– 7.0 –––
tr Rise Time ––– 6.6 –––
td(off) Turn-Off Delay Time ––– 13 ––– ns
tf Fall Time ––– 3.1 –––
Ciss Input Capacitance ––– 810 –––
Coss Output Capacitance ––– 100 ––– pF
Crss Reverse Transfer Capacitance ––– 15 –––
Coss Effective Output Capacitance ––– 97 –––
LD Internal Drain Inductance ––– 4.5 ––– Between lead, 
nH 6mm (0.25in.)
LS Internal Source Inductance ––– 7.5 ––– from package
Diode Characteristics �
 Parameter Min. Typ. Max. Units
IS @ TC = 25°C Continuous Source Current ––– ––– 8.7
(Body Diode) A
ISM Pulsed Source Current ––– ––– 34
(Body Diode)��
VSD Diode Forward Voltage ––– ––– 1.3 V
trr Reverse Recovery Time ––– 57 86 ns
Qrr Reverse Recovery Charge ––– 140 210 nC
ID = 5.2A
ƒ = 1.0MHz, See Fig.5
TJ = 25°C, IF = 5.2A
di/dt = 100A/µs �
TJ = 25°C, IS = 5.2A, VGS = 0V �
showing the
integral reverse
p-n junction diode.
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA 
VGS = 10V, ID = 5.2A �
VDS = VGS, ID = 50µA
VDS = 150V, VGS = 0V
VGS = 0V, VDS = 0V to 120V 
VDS = 150V, VGS = 0V, TJ = 125°C
VGS = 20V
VGS = -20V
VGS = 10V 
ID = 5.2A
VGS = 0V
MOSFET symbol
RG = 2.4Ω
VDS = 50V, ID = 5.2A
Conditions
and center of die contact 
VDD = 75V, VGS = 10V��
VDS = 75V
VDS = 25V
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Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature
Fig 6. Typical Gate Charge vs.Gate-to-Source VoltageFig 5. Typical Capacitance vs.Drain-to-Source Voltage
0.1 1 10 100
VDS, Drain-to-Source Voltage (V)
0.01
0.1
1
10
100
I D
, D
ra
in
-t
o-
S
ou
rc
e 
C
ur
re
nt
 (
A
)
≤ 60µs PULSE WIDTH
Tj = 25°C
5.5V
VGS
TOP 15V
12V
10V
9.0V
8.0V
7.0V
 6.0V
BOTTOM 5.5V
1 10 100 1000
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
10000
100000
C
, C
ap
ac
ita
nc
e 
(p
F
)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd 
Coss = Cds + Cgd
0 5 10 15 20
 QG Total Gate Charge (nC)
0
4
8
12
16
20
V
G
S
, G
at
e-
to
-S
ou
rc
e 
V
ol
ta
ge
 (
V
) VDS= 120V
VDS= 75V
VDS= 30V
ID= 5.2A
0.1 1 10 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
I D
, D
ra
in
-t
o-
S
ou
rc
e 
C
ur
re
nt
 (
A
)
≤ 60µs PULSE WIDTH
Tj = 150°C
5.5V
VGS
TOP 15V
12V
10V
9.0V
8.0V
7.0V
 6.0V
BOTTOM 5.5V
-60 -40 -20 0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
0.0
0.5
1.0
1.5
2.0
2.5
R
D
S
(o
n)
 , 
D
ra
in
-t
o-
S
ou
rc
e 
O
n 
R
es
is
ta
nc
e 
 
 
 
 
 
 
 
 (
N
or
m
al
iz
ed
)
ID = 5.2A
VGS = 10V
4 5 6 7 8
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
I D
, D
ra
in
-t
o-
S
ou
rc
e 
C
ur
re
nt
 (Α
)
VDS = 50V
≤ 60µs PULSE WIDTH
TJ = 25°C
TJ = 175°C
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area
Fig 10. Threshold Voltage vs. Temperature
25 50 75 100 125 150
TJ , Junction Temperature (°C)
0
2
4
6
8
10
I D
 
, D
ra
in
 C
ur
re
nt
 (
A
)
0.0 0.5 1.0 1.5
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
I S
D
, R
ev
er
se
 D
ra
in
 C
ur
re
nt
 (
A
)
TJ = 25°C
TJ = 150°C
VGS = 0V
-75 -50 -25 0 25 50 75 100 125 150
TJ , Temperature ( °C )
2.0
3.0
4.0
5.0
V
G
S
(t
h)
 G
at
e 
th
re
sh
ol
d 
V
ol
ta
ge
 (
V
)
ID = 50µA
1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
T
he
rm
al
 R
es
po
ns
e 
( 
Z 
th
JC
 ) 0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W) τι (sec)
1.508254 0.000814
2.154008 0.111589
3.237738 2.2891
τJ
τJ
τ1
τ1
τ2
τ2 τ3
τ3
R1
R1 R2
R2 R3
R3
τ
τC
Ci= τi/Ri
Ci= τi/Ri
1 10 100 1000
VDS , Drain-toSource Voltage (V)
0.1
1
10
100
I D
, 
D
ra
in
-t
o-
S
ou
rc
e 
C
ur
re
nt
 (
A
)
Tc = 25°C
Tj = 150°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA 
LIMITED BY RDS(on)
100µsec
DC
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Fig 13. Maximum Avalanche Energy Vs. Drain CurrentFig 12. On-Resistance Vs. Gate Voltage
4 5 6 7 8 9 10
VGS, Gate-to-Source Voltage (V)
0.0
0.1
0.2
0.3
0.4
0.5
R
D
S
(o
n)
, 
D
ra
in
-t
o 
-S
ou
rc
e 
O
n 
R
es
is
ta
nc
e 
(Ω
)
TJ = 25°C
TJ = 125°C
ID = 5.2A
25 50 75 100 125 150
Starting TJ,Junction Temperature (°C)
0
50
100
150
200
250
300
350
E
A
S
, 
S
in
gl
e 
P
ul
se
 A
va
la
nc
he
 E
ne
rg
y 
(m
J) I D
TOP 0.91A
 1.1A
BOTTOM 5.2A
Fig 14. ��
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P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple ≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P.W.Period
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Fig 16a. Switching Time Test Circuit Fig 16b. Switching Time Waveforms
VGS
VDS
90%
10%
td(on) td(off)tr tf
Fig 15b. Unclamped Inductive WaveformsFig 15a. Unclamped Inductive Test Circuit
tp
V(BR)DSS
IAS
RG
IAS
0.01Ωtp
D.U.T
LVDS
+
- VDD
DRIVER
A
15V
20VVGS
Fig 17a. Gate Charge Test Circuit Fig 17b Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
1K
VCC
DUT
0
L
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Data and specifications subject to change without notice.
 This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 08/06
TO-220 Full-Pak 5-Pin Part Marking Information
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TO-220 Full-Pak 5-Pin Package Outline, Lead-Form Option 117
(Dimensions are shown in millimeters (inches))
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Note: For the most current drawings please refer to the IR website at: 
http://www.irf.com/package/ 
 
 
IMPORTANT NOTICE
The information given in this document shall in no 
event be regarded as a guarantee of conditions or 
characteristics (“Beschaffenheitsgarantie”) . 
With respect to any examples, hints or any typical 
values stated herein and/or any information 
regarding the application of the product, Infineon 
Technologies hereby disclaims any and all 
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without limitation warranties of non-infringement 
of intellectual property rights of any third party. 
In addition, any information given in this document 
is subject to customer’s compliance with its 
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use of the product of Infineon Technologies in 
customer’s applications. 
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intended for technically trained staff. It is the 
responsibility of customer’s technical departments 
to evaluate the suitability of the product for the 
intended application and the completeness of the 
product information given in this document with 
respect to such application. 
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contact your nearest Infineon Technologies office 
(www.infineon.com).
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contain dangerous substances. For information on 
the types in question please contact your nearest 
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Except as otherwise explicitly approved by Infineon 
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